Staff Digital Verification Engineer

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Responsibilities

This is a full-time, on-site role for a Senior Hardware Verification Engineer using UVM, located at Hyderabad, India; The role involves developing and maintaining UVM-based verification environments, writing test benches, test cases, and coverage models for complex IP and SoC designs.; The engineer will analyze specifications, define verification plans, create and execute verification scenarios, and debug RTL issues in close collaboration with design, architecture, and firmware teams.; Daily tasks include running regressions, monitoring coverage metrics, performing root-cause analysis of failures, and contributing to continuous improvement of verification methodologies and automation.; The role may also include mentoring junior engineers, participating in design and verification reviews, and aligning verification activities with project schedules and quality standards.

Requirements

Bachelor's or master's degree in Electronics Engineering, Electrical Engineering or a related discipline.; 6 - 14 years of experience in Digital Verification with Strong expertise in System Verilog, UVM methodology and constrained-random verification.; Experience with Formal Verification techniques and tools to complement simulation-based verification - advantage.; Solid understanding of Computer Architecture, including memory hierarchies, bus protocols, and high-performance compute subsystems.; Proficiency with verification tools and flows (e.g., simulators, waveform viewers, coverage tools, regression management, scripting in Python/Perl/Tcl).; Effective communication and collaboration skills, with the ability to work in cross-functional, multicultural teams.; Experience in semiconductor product development for automotive, industrial, or embedded systems is an advantage; Strong English, availability to support and cooperate with external teams including Business travels.; Experience using AI tools to accelerate code development, debugging, and improvement is an advantage.