Staff FPGA Engineer

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.

We are seeking a highly skilled FPGA Engineer to focus on the critical communication paths of our security processor. This role is central to ensuring that our hardware interacts seamlessly and securely with the broader server ecosystem (BIOS, BMC, and Host). You will be responsible for implementing OEM-specific logic and performing rigorous end-to-end validation across high-speed serial interfaces.

Responsibilities

End-to-End Testing: Validate high-speed SPI, eSPI, and LTPI interfaces between the security processor, BIOS, and BMC to ensure absolute signal integrity and strict protocol compliance across all power states.; OEM Mode Logic: Design, implement, and verify specialized FPGA logic to support OEM mode configurations and secure manufacturing/provisioning flows.; Project & Tooling Integration: Utilize and extend project-based workflows for hardware description and verification, ensuring that FPGA designs are integrated into the wider system-level CI/CD and simulation environments.; Vendor & Ecosystem Collaboration: Demonstrate the ability to communicate effectively with IP vendors to resolve complex integration issues and develop customized application layers tailored to Axiado’s unique security architecture.; Hardware Debugging: Utilize high-speed oscilloscopes, logic analyzers, and internal FPGA debugging tools (e.g., Vivado ILA) to identify and fix physical layer and protocol-level bottlenecks.

Requirements

Protocol Expertise: Deep hands-on experience with SPI, eSPI, LTPI, and I2C/I3C protocols, including an understanding of timing requirements and electrical characteristics.; FPGA Design: Proficiency in Verilog or SystemVerilog for targeting Xilinx, Intel, or Lattice FPGA architectures.; Application Development: Familiarity with customized application development at the hardware-software interface, allowing for flexible implementation of proprietary features.; Communication: Strong technical communication skills to act as the primary point of contact for external IP providers and internal firmware teams.; Education: BS/MS in Electrical Engineering, Computer Engineering, or a related technical field.

Nice to have

Experience with Open Compute Project (OCP) DC-SCM standards.; Understanding of Root of Trust (RoT) and secure hardware handoff sequences.; Familiarity with Project-based workflows or similar modern hardware description methodologies.