Principal Silicon Design Methodology Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses, including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally. As Microsoft's cloud business continues to grow, the Front-End CAD team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Silicon Design Methodology Engineer to join the FE CAD team.

Responsibilities

Own one or more libraries' design/qualification end to end, including specification, RTL/behavioral modeling, verification, static qualifications and release; Drive front-end qualification of library IPs through Lint, CDC, RDC, synthesis and low-power checks to clean, reproducible, multi-project releases; Build and maintain qualification and regression pipelines for library, triage failures, root cause and drive them to closure; Act as the front-line technical owner for partner-reported issues against library IP, reproducing against standalone libraries and delivering fixes with a predictable turnaround; Partner with SoC design, DV, methodology, physical design and EDA vendor teams to align library behavior, qualification criteria and release readiness; Provide functional leadership to a team of front-end CAD engineers: set technical direction, review designs and PRs, mentor engineers, and improve backlog, sprint and release hygiene; Communicate status, risk and release readiness clearly to engineering leadership and partner stakeholders across time zones

Requirements

BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience; At least 6 years of experience in front-end digital design and development; At least 2 years of experience taking IP through front-end qualification, including lint, clock-domain crossing (CDC), reset-domain crossing (RDC), synthesis, and low-power checks, and release; Understanding of standard cells mapping, memories, and behavioral design modeling; Ability to analyze the functionality and connectivity of existing IP and implement incremental design improvements; Hands-on experience with IP design simulation and debugging workflows; Ability to meet Microsoft, customer and/or government security screening requirements, including the Microsoft Cloud Background Check

Nice to have

MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience; 6+ years of relevant experience; End-to-end ownership of shared design/verification libraries and multi-project consumption; Knowledge of the front-end VLSI design lifecycle, with demonstrated contributions to design methodology improvements; Experience developing and maintaining CI/CD pipelines for design and verification workflows; Experience applying AI-assisted techniques to improve design and verification productivity; Demonstrated technical leadership and mentoring skills